The present invention relates to a nonvolatile memory and, more particularly, to a semiconductor device having a double-well structure and a method for manufacturing the same.
A device such as a nonvolatile memory, in which a positive or negative potential is applied to a word line of a memory cell when data is written or erased, includes two MOSFETs of different conductivity-types in part of a peripheral circuit of the memory cell. Underlying substrates on which these MOSFETs are formed have to be electrically separated from each other. ISSCC 92, xe2x80x9cA 5V-Only 0.6 xcexcm Flash EEPROM with Row Decoder Scheme in Triple-Well Structurexe2x80x9d discloses a method for separating a semiconductor substrate and a well of the same conductivity type as that of the substrate from each other, as illustrated in FIGS. 26 to 30.
Referring to FIG. 26, a silicon oxide film 702 is formed on a P-type silicon semiconductor substrate 701, and a resist pattern 703 having an opening 703a corresponding to an N-type well forming region is formed on the silicon oxide film 702. Using the resist pattern 703 as a mask, phosphorus ions 720 are implanted into the substrate 701.
The resist pattern 703 is removed and, as shown in FIG. 27, a plurality of silicon oxide films 704 for isolating elements are formed on the surface of the substrate 701. Moreover, the phosphorus ions 720 are activated to form an N-type well 705 in the substrate 701, and then a resist pattern 706 having an opening 706a corresponding to a P-type well forming region is formed on the substrate 701. Using the resist pattern 706 as a mask, boron ions 721 are implanted into the substrate 701.
The resist pattern 706 is removed and, as illustrated in FIG. 28, the boron ions 721 are activated to form a P-type well 707 in the substrate 701, and then a resist pattern 708 having an opening 708a corresponding to a PMOSFET forming region in the N-type well 705 is formed. Using the resist pattern 708 as a mask, for example, phosphorus ions 722 are implanted into the substrate 701.
The resist pattern 708 is removed and, as shown in FIG. 29, a gate oxide film 709 and a gate electrode wiring pattern 710 are formed and then N- and P-type diffusion layers 711 and 712 serving as source and drain regions are formed.
In the semiconductor device manufactured by the above-described method, the P-type well 707 and P-type silicon substrate 701 are electrically isolated from each other since the P-type well 707 is surrounded with the N-type well 705. However, the semiconductor device has the following drawback.
A number of phosphorus ions 720, which are implanted when the N-type well 705 is formed, are present on the surface of the substrate 701. Thus, the boron ions 721 enough to cancel the phosphorus ions 720, have to be implanted in order to form the P-type well 707. On the surface of the P-type well 707 so formed, there are phosphorus ions 720 and boron ions 721 the number of which is larger than that of the ions 720, with the result that a large number of impurities will be included in a region within the P-type well 707 where a channel of the MOSFET is to be formed. It is thus well-known that the carrier mobility is lowered by the impurity scattering effect and the MOSFET cannot be switched at high speed.
FIG. 30 is a profile of a three-layered structure of the P-type well 707, N-type well 705 and P-type silicon substrate 701.
To compensate for the above drawback, there is a method for restricting-the concentration of the phosphorus ions used for forming the N-type well 705 to a relatively low value. Naturally, the capability of separating the P-type well 707 and P-type semiconductor substrate 701 is lowered and thus a difference in potential therebetween cannot be sufficiently secured. Furthermore, the N-type well 705 has a PMOSFET forming region on its surface, and it is evident from the scaling rule that if its underlying substrate is low in impurity concentration, the PMOSFET cannot be miniaturized. Consequently, a step of implanting high-concentration phosphorus ions into the PMOSFET forming region on the N-type well 705, using the resist pattern 708 shown in FIG. 28, is essential for increasing the PMOSFET forming region in impurity concentration. This is however a factor in causing a great cost due to an increase in manufacturing step.
The profile of the channel of an NMOSFET formed on the surface of the P-type well 707 is a complicated one representing a mixture of phosphorus ions for forming the N-type well 705 and boron ions for forming the P-type well 707 and controlling the channel. The complicated profile varies the threshold voltage Vth of the NMOSFET, reduces the circuit margin, and decreases the yield.
In the foregoing conventional semiconductor device which necessitates electrically separating the semiconductor substrate and the well of the same conductivity type as that of the substrate, a number of impurities of two different types are mixed on the surface of the well. For this reason, neither the semiconductor substrate and well can be separated from each other nor the high performance of the MOSFET formed in the well can be achieved. To enhance the performance of the MOSFET, the number of masks is increased and so is the number of steps of forming and removing the masks, thus causing a problem of variations in characteristics of the MOSFET formed in the well having a conductivity type opposite to that of the semiconductor substrate.
It is accordingly an object of the present invention to provide a high-performance semiconductor device achieved by controlling its profile and a method for manufacturing the same at low cost.
To attain the above object, there is provided a semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first well of the first conductivity type formed on a surface region of the semiconductor substrate; and
a second well of a second conductivity type formed in the semiconductor substrate so as to surround the side of the first well and the bottom thereof,
wherein if the concentration of impurities of the second conductivity type in the first well is D1 and the concentration of impurities of the second conductivity type in the second well is D2, D1 less than D2.
According to the semiconductor device so constituted, the second well electrically isolates the semiconductor substrate and first well from each other. Since no impurities of a conductivity type opposite to that of the substrate are present on the surface of the first well, other impurities are not required to cancel the impurities of the opposite conductivity type. Thus, the total sum of impurities of a channel region of a MOSFET formed in the first well is decreased, with the result that the MOSFET is improved in driving performance to allow a high-speed operation.
There is also provided a method for manufacturing a semiconductor device, comprising:
a first step of implanting first conductivity type impurity ions and second conductivity type impurity ions at least in a first well forming region of a semiconductor substrate of a first conductivity type to different depths, the first conductivity type impurity ions constituting a first well;
a second step of implanting the second conductivity type impurity ions in a region around the first well forming region, the second conductivity type impurity ions implanted in the second step and the second conductivity type impurity ions implanted in the first step constituting a second well; and
a third step of activating the first conductivity type impurity ions and the second conductivity type impurity ions to form the first well and the second well in the semiconductor substrate.
According to the manufacturing method described above, when the first and second wells are formed, the impurity ions of the same conductivity type as that of the semiconductor substrate and those of the conductivity type opposite to that of the substrate, are implanted into the first well forming region. These impurity ions are implanted into the substrate to their different depths by varying acceleration energy. The concentration of impurities for forming the second well in the first well can thus be lowered.
The mask for forming the first well can be used for forming part of the second well. Thus, the number of masks can be reduced.
In the second step, the concentration of the second impurity ions implanted into the substrate can be controlled. There is a strong possibility that the region to which the impurity ions are implanted in the second step will be a MOSFET forming one, and the device can be miniaturized by controlling the concentration of the impurities of the region.
Since, furthermore, no step of controlling the impurity concentration of the MOSFET forming region is required, the manufacturing costs can be decreased.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.